1. Field of the Invention
This invention relates to a process for producing a semiconductor memory device, more particularly to a process for producing a DRAM (Dynamic Random Access Memory) employing a one-transistor type memory cell which provides both high integration and increased capacitance.
2. Description of the Related Art
Higher integration of semiconductor memory devices is desirable with the recent demand for semiconductor memory devices with larger capacities. The DRAM among other semiconductor memory devices has been concentrated on extensively as it is frequently a symbol of advancement in integration technology.
DRAM memory cells are grouped into one-transistor type, three-transistor type and four-transistor type cells, depending on the number of transistors used in the memory cell. The one-transistor type memory cell consists merely of one MOS capacitor for storing and thereby memorizing electric charge and one MOS transistor for transferring the electric charge. Accordingly, the construction of such a memory cell is simple and has a compact size compared with other types of memory cells. One-transistor type memory cells are generally employed in DRAMs of 4K bits or more.
Recently, evolution in DRAM technology has increased dramatically. 4M Bit and 16M Bit DRAMs are already commercially available, and 64M Bit and even 256M Bit DRAMs are now manufactured on experimental bases. One important thing in producing such large capacity DRAMs is to minimize chip size thereby reducing the size of the memory cells. One way to accomplish this is through higher integration which, in turn, achieves higher density memory cells. In order to attain this object, one-transistor type memory cells may be employed so as to reduce the size of the MOS capacitor. However, taking soft errors which must be avoided and noise margin which must be secured into consideration, it is preferable to increase capacitance of the capacitor. It is difficult to both reduce the volume and increase capacitance of a capacitor.
Capacitance C can be expressed by the following equation: EQU C=.epsilon..sub.0 .epsilon..sub.5 .multidot.A/d (1)
where .epsilon..sub.0 is permittivity in a vacuum; .epsilon..sub.5 is the dielectric constant of dielectric medium (capacitor insulating layer) between the electrodes; A is the electrode area; and d is the thickness of the dielectric layer.
From the equation (1), the following methods can be given so as to increase capacitance while reducing the size of MOS capacitor:
(1) to increase the dielectric constant of the dielectric layer; PA1 (2) to reduce the thickness of the dielectric layer; and PA1 (3) to increase the electrode area by allowing the MOS capacitor to have a three-dimensional structure.
In the first method, it can be considered to use a dielectric layer having a high dielectric constant. However, such high dielectric layers are now under development and not in production. If the second method is used, as the size of the memory cell is reduced the thickness of the dielectric layer becomes extremely small and pinholes are readily formed therein. Thus, the second method is not practical from the standpoint of reliability. Under such circumstances, a combination of the second method and the third method is being studied, in which an MOS capacitor is allowed to have a three-dimensional structure to increase electrode area and the thickness of the dielectric layer is reduced as much as possible.
Referring to the structure of the one-transistor type memory cell, planar memory cells have widely been used. However, the area occupied by the memory cell increases in a planar memory cell as the electrode area is increased. Thus, it was attempted to increase the electrode area by allowing the MOS capacitor to have a three-dimensional structure, and stacked type memory cells and trenched type memory cells have been proposed.
The stacked type memory cell has a polysilicon multi-layered structure formed on a substrate. In producing such stacked type memory cells, the MOS capacitor is fabricated according to 3-layer polysilicon technology using a first polysilicon layer as a gate electrode (word line). This dielectric layer is disposed between a second polysilicon layer and a third polysilicon layer. Accordingly, the electrode area can be increased by increasing the film thickness of the storage electrode (storage node) formed by the second polysilicon layer, particularly by means of increasing the side wall area.
In producing a trenched type memory cell, perpendicular trenches, which are filled with polysilicon, are formed in a substrate, and an MOS capacitor is formed between the substrate and the polysilicon layer. Since the MOS capacitor is formed on the inner wall surfaces of the trenches, the electrode area can be increased without increasing the area of the memory cell.
However, the stacked type memory cell involves a problem that the aspect ratio of the storage electrode increases as the size of the memory cell is reduced to form steps on the surface of the memory cell. Such steps formed on the surface of the memory cell not only make it difficult to uniformly form a wiring layer thereon but also are liable to cause disconnection in the wiring layer formed. Meanwhile, in the trenched type memory cell, the pitch between the trenches becomes narrow as the size of the memory cell is reduced to disadvantageously increase the leakage current between the trenches. Therefore, even the stacked or trenched type memory cells have encountered a borderline of up to 16M bit DRAMs.
Under such circumstances, a stacked trenched combined type memory cell which is a combination of the stacked type memory cell and the trenched type memory cell was proposed as disclosed in Japanese Unexamined Patent Publication No. 116160/1990 with a view to producing a capacity of 64M bits or more. However, in such stacked-trenched combined type memory cell, a storage electrode of polysilicon layer having a predetermined thickness is formed along the inner wall surface of the trenches. Then a dielectric layer and an opposite electrode are formed successively thereon. Accordingly, the internal surface area of the storage electrode becomes smaller as the size of the memory cell is reduced to disadvantageously reduce capacitance during the steps of successive formation of the dielectric layer and the opposite electrode.
With a view to solving the above problem, a stacked-trenched combined type memory cell as disclosed in Japanese Unexamined Patent Publication No. 3-190162 (hereinafter referred to as improved stacked-trenched combined type memory cell) was proposed. The outline of the process for producing a stacked-trenched combined type memory cell will now be described with reference to FIGS. 13 through 20.
Referring now to FIG. 13 there is shown a process of forming an MOS transistor and a first photoresist pattern PR11 on a P-type semiconductor substrate 100. A field oxide layer 101 is first formed on the semiconductor substrate 100 to define an active region on which a gate oxide layer 102 is then formed. Subsequently, an impurity-doped polysilicon gate electrode (word line) 103 is further formed on the gate oxide layer 102. A word line 104 is formed on the field oxide layer 101 at a position adjacent to the gate electrode 103. The word line 104 is formed using an impurity-doped polysilicon similar to gate electrode 103. An N-type impurity is injected in the surface of the semiconductor substrate on each side of the gate electrode 103 to provide a source region 105 and a drain region 106. A first insulating layer 107 is formed over the entire surface of the resulting structure. Then first photoresist pattern PR11 is formed on insulating layer 107.
The first photoresist pattern PR11 thus formed is subsequently used as an etching mask to carry out etching of predetermined portions of the first insulating layer 107 formed on the source region 105 to expose partly the source region 105.
Referring now to FIG. 14 there is shown a process of forming a polysilicon layer 108 to be used as the storage electrode of the MOS capacitor and a second photoresist pattern PR12 as an etching mask for forming the storage electrode. The first photoresist pattern PR11 shown in FIG. 13 is first removed, and a polysilicon layer 108 is formed over the first insulating layer 107 and the exposed portion of the source region 105. Subsequently, a second photoresist pattern PR12 is formed on the polysilicon layer 108.
Referring now to FIG. 15 there is shown a process of forming a storage electrode pattern 108a, a second insulating layer OX and a third photoresist pattern PR13. The polysilicon layer 108 is first etched using the second photoresist pattern PR12 (shown in FIG. 14) as an etching mask to form a storage electrode pattern 108a, and then the second photoresist pattern PR12 is removed. Next, a low temperature oxide (LTO) layer or a high temperature oxide (HTO) layer is formed as a second insulating layer OX such that it covers the storage electrode pattern 108a. The third photoresist pattern PR13 is formed on the second insulating layer OX.
Referring now to FIG. 16 there is shown a process of forming a mask OXM as an etching mask for forming trenches. The second insulating layer OX is first etched using the third photoresist pattern PR13 (shown in FIG. 15) as an etching mask to form a mask OXM. The third photoresist pattern PR13 is then removed.
Referring now to FIG. 17 there is shown a process of forming a trench 109. The storage electrode pattern 108a, source region 105 and semiconductor substrate 100 are etched using the mask OXM as an etching mask to form a trench 109.
Referring now to FIG. 18 there is shown a process of forming a sacrificial oxide layer 110, which can be formed along the inner surface of the storage electrode pattern 108a and that of the trench 109 by thermal oxidation using the mask OXM as a seed.
Subsequently, the sacrificial oxide layer 110 is removed by BOE (buffered oxide etching), whereby not only the sharp corner at the bottom of the trench 109 can be rounded but also any irregularity such as the portion of the inner wall surface of the trench 109 damaged during formation thereof can be removed.
Referring now to FIG. 19 there is shown a process of impurity doping. A polysilicon layer 108b and an impurity doped region 111 can be formed by doping the storage electrode pattern 108a and the inner wall surface of the trench 109 with an N-type impurity. The polysilicon layer 108b and the impurity doping region 111 are used as the storage electrode of the MOS capacitor.
Referring now to FIG. 20 there is shown a process of forming a dielectric layer 112 and an opposite electrode 113. A dielectric layer 112 having an oxide/nitride/oxide structure, a so-called ONO structure, is first formed on the inner wall surface of the trench 109 including the surfaces of polysilicon layer 108b and the impurity doped region 111. Then, a polysilicon layer is further formed as an opposite electrode 113 on the first insulating layer 107 and the dielectric layer 112 so as to fill up the trench 109.
Thus, in such improved stacked-trenched combined type memory cell, the polysilicon layer 108b and the impurity doped region 111 are utilized as the storage electrode of the MOS capacitor. Accordingly, a large storage electrode area can be achieved, compared with the process for forming a storage electrode using a polysilicon layer having a predetermined thickness along the inner wall surface of the trench (as disclosed in Japanese Unexamined Patent Publication No. 116160/1990), to provide greater capacitance.
However, the process for producing the improved stacked-trenched combined type memory cells is complicated and thus costly. The trench 109 cannot be formed without going through the step of forming a third photoresist pattern PR13 as shown in FIG. 15, a step of forming a mask OXM as shown in FIG. 16 and the step of subjecting the storage electrode pattern 108a, the source region 105 and the semiconductor substrate 100 to anisotropic etching as shown in FIG. 17. Thus, in order to form a trench 109 accurately in position, the anisotropic etching of the second insulating layer OX must be accurately controlled after the profile of the photoresist pattern PR13 is accurately controlled. The anisotropic etching of the storage electrode pattern 108a, source region 105 and the semiconductor substrate 100 must also be controlled accurately. However, it is difficult to achieve such controls accurately, and there occurs a problem that the trench 109 is liable to be formed out of position. This can cause fatal defects especially in the conventional improved stacked-trenched combined type memory cell as the memory cell has less capacitance.
This invention is proposed in order to solve the above problems, and it is an object of the invention to provide a simple process for producing an improved stacked-trenched combined type memory cell. It is another object of the invention to provide a process for producing an improved stacked-trenched combined type memory cell in which the trench can be efficiently formed.